Issue No.11 - November (2007 vol.56)
R.A. Patel , Univ. of Sheffield, Sheffield
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70750
Novel modulo 2n-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area times delay2 and energy times delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology.
residue number systems, adders, parallel architectures,parallel-prefix architecture, CMOS technology, VLSI design, residue number system, addition algorithm, single representation,Adders, Computer architecture, Delay, Logic gates, Complexity theory, Periodic structures, Chromium,VLSI design, Modulo 2n-1 adders, One's complement adders, parallel-prefix adders, computer arithmetic
R.A. Patel, M. Benaissa, S. Boussakta, "Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero", IEEE Transactions on Computers, vol.56, no. 11, pp. 1484-1492, November 2007, doi:10.1109/TC.2007.70750