Issue No. 11 - November (2007 vol. 56)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70740
The main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a power-aware cached-dynamic-RAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce power consumption. We modify the operation and structure of CDRAM with the goal of reducing energy consumption while retaining the performance advantage for which CDRAM was originally proposed. In this paper, we describe our PA-CDRAM organization and show how to incorporate it into the Rambus memory. We evaluate the approach using a cycle-accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to 84 percent (28 percent on the average) improvement in the energy-delay product and up to 76 percent (19 percent on the average) savings in energy when compared to a time-out power management technique.
cache storage, power aware computing, random-access storage,near-memory caching, energy consumption, power reduction, energy reduction, power-aware cached-dynamic-RAM, PA-CDRAM, cycle-accurate processor, memory simulator,Random access memory, Memory management, Protocols, Bandwidth, Arrays,Memory design, Power Management, Energy-aware systems, Memory power management, Cached DRAM
"Near-Memory Caching for Improved Energy Consumption", IEEE Transactions on Computers, vol. 56, no. , pp. 1441-1455, November 2007, doi:10.1109/TC.2007.70740