Issue No. 10 - October (2007 vol. 56)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.1085
This paper deals with the issue of developing efficient algorithms for reconfiguring two-dimensional VLSI arrays linked by four-port switches in the presence of faulty processing elements (PEs). The proposed algorithm reroutes the arrays with faults in both row and column directions at the same time. Unlike previous work, the compensation technique to replace the faulty PE is not restricted to the adjacent rows of the excluded row. Instead, we consider the neighbor rows of any faulty PE for compensation purposes. The nonfaulty PEs lying in the excluded rows are also effectively utilized to form the maximal target arrays, making the proposed algorithm more efficient in terms of both the percentages of harvest and the degradation of VLSI arrays for random and clustered faults. Empirical study shows that the improvement in harvest increases with increasing fault size and is more notable for maximal square target arrays than for maximal target arrays. Our investigations show that the improvement can be up to 8 percent and 23 percent for a 256 times 256 VLSI array with random faults of size 25 percent for maximal target arrays and for maximal square target arrays, respectively.
arrays, fault tolerance, semiconductor switches, VLSI,VLSI arrays reconfiguration, integrated row, column rerouting, four-port switches, faulty processing elements, maximal square target arrays,Logic arrays, Algorithm design and analysis, Redundancy, Fault tolerance, Degradation, Very large scale integration, Clustering algorithms,Degradable VLSI array, reconfiguration, faulttolerance, algorithm, routing
"Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches", IEEE Transactions on Computers, vol. 56, no. , pp. 1387-1400, October 2007, doi:10.1109/TC.2007.1085