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We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n\log n); previous approaches needed a time of O(n^{2}) for correct results and O(n) for heuristic results. We also show a matching lower bound of \Omega(n\log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with \Theta(n\log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior.
Reconfigurable hardware, field-programmable gate array (FPGA), module placement, free-space manager, routing-conscious placement, geometric optimization, line-sweep technique, optimal runtime, lower bounds.

J. Teich, C. Bobda, A. Ahmadinia, J. C. van der Veen and S. P. Fekete, "Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices," in IEEE Transactions on Computers, vol. 56, no. , pp. 673-680, 2007.
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