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Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2^{n}-(2^{n - 2} + 1) addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130nm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space.
Computer arithmetic, modular adder, parallel-prefix adder, residue number system, VLSI.
M. Benaissa, S. Boussakta, R.A. Patel, "Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS", IEEE Transactions on Computers, vol. 56, no. , pp. 572-576, April 2007, doi:10.1109/TC.2007.1001
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