Issue No. 04 - April (2007 vol. 56)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.1013
John D. Villasenor , IEEE
Dong-U Lee , IEEE
We present an automated bit-width optimization methodology for polynomial-based hardware function evaluation. Due to the analytical nature of the approach, overflow protection and precision accurate to one unit in the last place (ulp) can be guaranteed. A range analysis technique based on computing the root of the derivative of a signal is utilized to determine the minimal number of integer bits. Fractional bit requirements are established using an analytical error expression derived from the functions that occur along the data path. Global fractional bit optimization across multiple computation stages is performed using simulated annealing and circuit area estimation functions.
Computer arithmetic, elementary function approximation, field programmable gate arrays, finite wordlength effects, minimax approximation and algorithms.
John D. Villasenor, Dong-U Lee, "A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation", IEEE Transactions on Computers, vol. 56, no. , pp. 567-571, April 2007, doi:10.1109/TC.2007.1013