Issue No. 04 - April (2007 vol. 56)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.1008
Jin-soo Kim , IEEE
Power consumed by memory systems becomes a serious issue as the size of the memory installed increases. With various low power modes that can be applied to each memory unit, the operating system can reduce the number of active memory units by collocating active pages onto a few memory units. This paper presents a memory management scheme based on this observation, which differs from other approaches in that all of the memory space is considered, while previous methods deal only with pages mapped to user address spaces. The buffer cache usually takes more than half of the total memory and the pages access patterns are different from those in user address spaces. Based on an analysis of buffer cache behavior and its interaction with the user space, our scheme achieves up to 63 percent more power reduction. Migrating a page to a different memory unit increases memory latencies, but it is shown to reduce the power consumed by an additional 4.4 percent.
Buffer cache, energy management, PAVM, SDRAM.
J. Lee, M. Lee, E. Seo and J. Kim, "PABC: Power-Aware Buffer Cache Management for Low Power Consumption," in IEEE Transactions on Computers, vol. 56, no. , pp. 488-501, 2007.