Issue No. 09 - September (2006 vol. 55)

ISSN: 0018-9340

pp: 1211-1215

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.146

ABSTRACT

In this paper, we present a bit-parallel multiplier for GF(2^m) defined by an irreducible pentanomial x^m+x^{k_3}+x^{k_2}+x^{k_1}+1, where 1\leq k_1 < k_2 <k_3\leq m/2. In order to design an efficient bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction matrix presented by Reyhani-Masoleh and Hasan. As a result, the time complexity of the proposed multiplier is T_A + (3+ \lceil \log _2(m-1)\rceil)T_X, where T_A and T_X are the delay of one AND and one XOR gate, respectively. This result matches or outperforms the previously known results. On the other hand, the proposed multiplier has the same space complexity as the previously known multipliers except for special types of irreducible pentanomials. Note that its hardware architecture is similar to that presented by Reyhani-Masoleh and Hasan.

INDEX TERMS

Bit-parallel multiplier, finite field arithmetic, shifted polynomial basis, irreducible pentanomial.

CITATION

D. Hong, K. Chang and S. Park, "Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis," in

*IEEE Transactions on Computers*, vol. 55, no. , pp. 1211-1215, 2006.

doi:10.1109/TC.2006.146

CITATIONS