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In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field.
Finite fields, polynomial basis multiplier, error detection.
M. Anwar Hasan, Arash Reyhani-Masoleh, "Fault Detection Architectures for Field Multiplication Using Polynomial Bases", IEEE Transactions on Computers, vol. 55, no. , pp. 1089-1103, September 2006, doi:10.1109/TC.2006.147
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