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Issue No. 08 - August (2006 vol. 55)
ISSN: 0018-9340
pp: 1062-1066
This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.
Computer arithmetic, high-speed arithmetic algorithms, combinational logic, overflow detection, multiplication.

M. J. Schulte, M. G. Arnold and M. Gok, "Integer Multipliers with Overflow Detection," in IEEE Transactions on Computers, vol. 55, no. , pp. 1062-1066, 2006.
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