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Real-time logic (RTL) [2], [3], [4] is useful for the verification of a safety assertion with respect to the specification of a real-time system. Since the satisfiability problem for RTL is undecidable, the systematic debugging of a real-time system appears impossible. A first step toward this challenge was presented in [1]. With RTL, each propositional formula corresponds to a verification condition. The number of truth assignments of a propositional formula can help us determine the specific constraints which should be added or modified to get the expected solutions. This paper solves an even more challenging problem specified as future work in [1], namely, the embedding and the integration of our debugger in autonomous systems which generate real-time control plans on-the-fly, since these specifications must meet timing constraints, but without human interaction. The idea is to consider in advance all the necessary information, such as the designer's guidance. We have implemented a tool (called ADRTL) that is able to perform automatic debugging. The confidence of our approach is high as we have successfully evaluated ADRTL on several existing industrial-based applications.
Real-time system, system development tools, automatic debugging, formal methods, timing constraint, counting SAT problem, incremental computation.

S. Andrei, A. M. Cheng, M. Lupu and W. N. Chin, "Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting," in IEEE Transactions on Computers, vol. 55, no. , pp. 830-842, 2006.
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