Issue No. 05 - May (2006 vol. 55)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.63
Jorge Garc?a-Vidal , IEEE
Lloren? Cerd? , IEEE
Mateo Valero , IEEE
We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.
Router architecture, packet buffers, high-performance memory systems, storage schemes.
J. Corbal, M. Valero, M. March, J. Garc?a-Vidal and L. Cerd?, "A DRAM/SRAM Memory Scheme for Fast Packet Buffers," in IEEE Transactions on Computers, vol. 55, no. , pp. 588-602, 2006.