Issue No. 05 - May (2006 vol. 55)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.76
Gian Carlo Cardarilli , IEEE
Adelio Salsano , IEEE
Marco Re , IEEE
Marco Ottavi , IEEE
In this paper, a methodology for the development of fault-tolerant adders based on the Radix 2 Signed Digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free” property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.
Fault tolerance, high-speed arithmetic, error checking.
Gian Carlo Cardarilli, Salvatore Pontarelli, Adelio Salsano, Marco Re, Marco Ottavi, "Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders", IEEE Transactions on Computers, vol. 55, no. , pp. 534-540, May 2006, doi:10.1109/TC.2006.76