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Continuous advances in silicon technology enable the development of complex System-on-Chip as cooperation among Digital Signal Processors (DPSs), General Purpose Processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC)—statically and in a fast manner—and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected Hardware-Software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.
System-on-Chip, embedded systems, multiprocessor systems, codesign, metrics, heterogeneous systems.

D. Sciuto, F. Salice, W. Fornaciari, L. Pomante and C. Brandolese, "Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC," in IEEE Transactions on Computers, vol. 55, no. , pp. 508-519, 2006.
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