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Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.
Design-for-testability, fault dominance, full-scan, overtesting, redundant faults, synchronous sequential circuits, test generation.

I. Pomeranz and S. M. Reddy, "On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan," in IEEE Transactions on Computers, vol. 55, no. , pp. 491-495, 2006.
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