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We demonstrate that the safe register abstraction is an inappropriate model of a shared bit variable in an ACM. This is due to the phenomenon of metastability and the way that circuits are engineered to reduce the probability of it propagating. We give a bit model that takes the engineered restrictions into account and which is therefore stronger than the safe bit model. With our bit model we show that some impossibility results concerning ACMs which are based on safe bit models are pessimistic. We establish this using the CSP process algebra and the FDR2 model-checker, by investigating the impact of various models of shared bits on different wait-free protocols, including Lamport's regular register, Simpson's 4-slot ACM, Kirousis et al.'s ACM, Tromp's Atomic Bit and 4-Track ACMs, and Haldar and Subramanian's ACM. We show how these protocols can fail in the presence of rereadable metastability.
Protocol verification, model checking, formal models, asynchronous operation.
James M. Armstrong, Neil Henderson, Stephen E. Paynter, "Metastability in Asynchronous Wait-Free Protocols", IEEE Transactions on Computers, vol. 55, no. , pp. 292-303, March 2006, doi:10.1109/TC.2006.42
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