Issue No. 03 - March (2006 vol. 55)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.32
Juan L. Arag? , IEEE Computer Society
Jos? Gonz?lez , IEEE Computer Society
Antonio Gonz?lez , IEEE Computer Society
Conventional front-end designs attempt to maximize the number of "in-flight” instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose Selective Throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).
Control speculation, energy-aware systems, low-power design, processor architecture.
Juan L. Arag?, Jos? Gonz?lez, Antonio Gonz?lez, "Control Speculation for Energy-Efficient Next-Generation Superscalar Processors", IEEE Transactions on Computers, vol. 55, no. , pp. 281-291, March 2006, doi:10.1109/TC.2006.32