Issue No. 03 - March (2006 vol. 55)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.38
Tomas Lang , IEEE Computer Society
In this paper, we present a novel algorithm and the corresponding architecture for performing range reduction, which is a preprocessing task required for the evaluation of some elementary functions such as trigonometric and exponential-based functions. The proposed algorithm introduces a modification to the Modular Range Reduction algorithm which increases the speed of computation and allows us to design an architecture for the floating-point case. The implementation presented admits as an input argument any representable number of the standard single precision IEEE 754 floating-point representation and provides the maximum accuracy to the final result. This supposes a hardware solution to the problem of having an input argument close to a multiple of the constant. A final comparison with other implementations is presented.
Range-reduction, elementary function evaluation, floating-point arithmetic.
J. Villalba, T. Lang and M. A. Gonzalez, "Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations," in IEEE Transactions on Computers, vol. 55, no. , pp. 254-267, 2006.