Issue No. 02 - February (2006 vol. 55)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.31
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.
Index Terms- Built-In Self Test (BIST), compaction, compression, testing, XPAND.
Subhasish Mitra, Kee Sup Kim, "XPAND: An Efficient Test Stimulus Compression Technique", IEEE Transactions on Computers, vol. 55, no. , pp. 163-173, February 2006, doi:10.1109/TC.2006.31