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Issue No. 02 - February (2006 vol. 55)
ISSN: 0018-9340
pp: 137-149
A flexible test architecture for embedded cores and all interconnects in a System-on Chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated.
Index Terms- System-on-chip test, cores, test access mechanism, design for testability.

D. Kagaris, S. Kuriakose and S. Tragoudas, "InTeRail: A Test Architecture for Core-Based SOCs," in IEEE Transactions on Computers, vol. 55, no. , pp. 137-149, 2006.
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