It is with great pleasure that we introduce the special section on Design and Test of Systems-on-Chips (SoC) to the readership of the IEEE Transactions on Computers. This special section consists of eight papers that have been selected to cover a wide spectrum of techniques and applications which are encountered in the design, manufacturing, assembly, and test of today's SoC. These papers are authored by outstanding researchers and cover experimental and speculative topics. As with all special sections, these topics are only representative of the publically available literature currently provided by the technical community.
Systems-on-a-Chip (SoC) represent a rapidly growing and promising field in the electronic and computer industry. Such tremendous growth is the result of significant advances in microelectronic technology that make it possible to build on the same silicon substrate complex systems, including electronic (analog, digital, and mixed mode), mechanical, optical, RF, and microwave cores, as well as sensors, actuators, and software-based systems. As a result, SoCs are very complex hardware/software systems, offering high-performance features. Examples of possible applications include wireless systems, real-time control systems, space exploration systems, and others. SoCs offer the inherent advantages in which computers and their digital domain can be merged to a variety of technologies and applications which, in the past, were attained at board-level. The design and test of such complex systems, however, still constitutes a major challenge.
From a design point of view, the ability to have a correctly functioning SOC depends on the ability to design and analyze a mixed-technology and to properly account for the interactions among the various cores. Proper management of interfaces between diverse cores and synchronization are examples of the problems to be faced. The unavailability of proper design and simulation tools for such complex systems and the limited resources for different technologies (such as mixed-signal systems) make such an effort rather difficult. The relation between the different modules of an SoC must be properly established using advanced techniques whose technological basis is just emerging. It is expected that these techniques will be highly inter and intradisciplinary in nature, thus involving designers with different backgrounds.
Configurability and programmability of the cores in an SoC suggest that wide applicability of these systems is indeed possible with great flexibility in integration. A further issue that designers are confronting is the evaluation of different configurations associated with the high density integration of cores. The merging of different technologies (such as digital and analog) on a single chip is also of high speculative interest because the manufacturing and organization of these systems is in its infancy. These new features must be evaluated at the early design stages because they have a considerable effect on the performance of SoCs as well as their viability for cost-effective implementation.
From a testing point of view, the development of proper test access mechanisms is one of the major challenges to be faced in the near future, as indicated also by the 1999 International Technology Roadmap for Semiconductors. The test access mechanisms must be compatible with the IEEE P1500 standard, which was developed for embedded core testing and which leaves the problem of the Test Access Mechanism (TAM) design to the system integrator. Several test access mechanisms have been proposed, including dedicated test bus, multiplexed access, etc., but the goal is to find a solution allowing the best trade-off between the test quality and cost (including the testing time). To evaluate test quality, however, complex failure mechanisms which might occur in such complex systems should also be evaluated. As an example, the possible occurrence of undesired coupling, noise, and skews between clock signals of diverse cores are some of the simplest failures which may affect the operation of the interfaces among the cores. Proper models, fault simulation tools, and test quality figures are needed. Testing time should also be reduced. In fact, while the design and test of SoCs requires a long time (similar to any computer system), the time-to-market of an SoC should be kept as short as possible to meet today's consumers' changing requirements.
The high performance possibly offered by the integration of complex systems on the same chip makes SoCs very promising for real-time applications, like control systems for automotive, avionic, space, chemical plants, etc. As an example, the first prototypes of SOCs, including electronic and mechanical cores, have already been employed by NASA for space exploration missions. Such a promising application potential, however, poses the problem of reliable design and verification as well as correct design and test. In the past, fault tolerance has been generally adopted to electronic systems for many critical mission applications. The possible adoption of fault tolerance techniques for SoCs (to include not only electronics, digital and analog, but also mechanical and optical cores) is an open problem that needs to be addressed in a timely manner.
The eight papers presented in this special section were chosen to adequately address these important SoC challenges. There are three papers dealing with the SOC design issues. The first paper is entitled "A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels" by A.D. Pimentel, C. Erbas, and S. Polstra. This paper gives insight into high-level modeling and simulation methods and provides practical means to explore a wide range of design choices. Dynamic voltage scaling provides an elegant solution to power consumption and heat dissipation problems of SoCs. The second paper, "Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling," by T. Phatrapornnant and M.J. Pont, addresses these issues in the context of a real-time embedded systems environment. The third paper, entitled "Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead," by M.-K. Chung and C.-M. Kyung, deals with the challenge of validating complex SoCs by using both hardware and software and simulation and emulation. The contribution of this paper is in the reduction of the communication overhead between mixed techniques by simulation and emulation, thus resulting in much improved speed for SoC validation.
The following three papers cover a wide range of timely SoC testing issues. The first paper is titled "InTeRail: A Test Architecture for Core-Based SOCs" by D. Kagaris, S. Tragoudas, and S. Kuriakose. This paper presents a test architecture that covers both the embedded cores and the interconnect. The TAM cost is minimized by exploiting testing parallelism and reusing the existing interconnects to form TAM paths. The second paper is "Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST" by X. Chen and M.S. Hsiao and presents a new architecture for spectral analysis based on Built-In Self-Test; a reduced test time is accomplished by allowing testing of a cluster of embedded sequential cores simultaneously. The test application time for the entire cluster, as well as the test data storage requirements, can be reduced significantly. The third paper dealing with SoC testing issues is "XPAND: An Efficient Test Stimulus Compression Technique" by S. Mitra and K.S. Kim. It presents an approach (namely, XPAND) to generate deterministic ATPG-based test patterns on-chip. These patterns, together with proper compaction techniques, allow us significantly to reduce SoC test data volume, test time, the number of tester channels, and test pins.
In addition to design and test, debugging is also a relevant issue for SOCs. The last two papers in this special issue specifically address this problem. The first paper is "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores" by A.B.T. Hopkins and K.D. McDonald-Maier. It defines interfaces to decouple the debug support and infrastructure from processor cores and active peripherals, thus allowing debug support reuse across heterogeneous SOC platforms. Finally, "A New Hybrid Fault Detection Technique for Systems-on-a-Chip," by P. Bernardi, L. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, and M. Violante, presents an Infrastructure IP to detect transient faults affecting data and code memory, as well as memory elements within a processor. It is a "hybrid" approach combining the benefits of hardware and software techniques.
We sincerely hope that this special section will be a reference publication for future research. The topics covered in the papers are timely and important and the authors have done an excellent job of presenting the material. We extend our sincere thanks to all the authors and reviewers. We also thank Dr. Viktor Prasanna, editor-in-chief of the IEEE Transactions on Computers, who allowed us to pursue this special section. Finally, a special thanks is due to all staff of the IEEE Computer Society publications office for editing and assembling this issue. Please feel free to contact us if you have questions or comments.
• J.-C. Lo is with the Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881. E-mail: firstname.lastname@example.org.
• C. Metra is with DEIS-University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy. E-mail: email@example.com.
• F. Lombardi is with the Department of Electrical and Computer Engineering, Northeastern University, 110 Forsyth Street, Building 309 Dana, Boston, MA 02115. E-mail: firstname.lastname@example.org.
For information on obtaining reprints of this article, please send e-mail to: email@example.com.
received the MS and PhD degrees in computer engineering from the University of Louisiana, Lafayette, Louisiana, in 1987 and 1989, respectively. Since 1989, he has been with the University of Rhode Island, where he is currently a professor and director of the Computer Engineering Program in the Department of Electrical and Computer Engineering. In 1999, he cofounded the Laboratory for Electronic Testing at the University of Rhode Island with support from the State of Rhode Island and Cherry Semiconductor Inc. He has served on program and steering committees of various IEEE conferences. He served as an associate editor of the IEEE Transactions on Computers
from 2001-2005. He has been working on concurrent error detection, fault-tolerant computing, dependable logic design synthesis, mixed-signal testing, on-chip power, and jitter measurement. He has published extensively in the above areas and holds two US patents.
received the degree (summa cum laude) in electronic engineering and the PhD degree in electronic engineering and computer science from the University of Bologna, Italy, where she is currently an associate professor in electronics. Dr. Metra is/has been a member of the steering and technical program committees of several international conferences. She is an associate editor of the IEEE Transactions on Computers
and Journal of Electronic Testing: Theory and Applications
and a member of the editorial board of the Microelectronics Journal
. Her research interests are in the field of design and test of digital systems, fault tolerance, online testing, reliable and error resilient systems, fault modeling, and concurrent diagnosis.
graduated in 1977 from the University of Essex, United Kingdom, with the BSc (Hons) degree in electronic engineering. In 1977, he joined the Microwave Research Unit at University College London, where he received the master's degree in microwaves and modern optics (1978), the Diploma in microwave engineering (1978), and the PhD degree from the University of London (1982). He is currently the holder of the International Test Conference (ITC) Endowed Professorship at Northeastern University, Boston. Since 2000, he has been the associate editor-in-chief of the IEEE Transactions on Computers
and an associate editor of IEEE Design and Test
. He also serves as the chair of the committee on "Nanotechnology Devices and Systems" of the Test Technology Technical Council of the IEEE. His research interests are testing and design of digital systems, quantum and nano computing, configurable/network computing, defect tolerance, and CAD VLSI. He has extensively published in these areas and edited six books.