Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation
Issue No. 12 - December (2005 vol. 54)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.199
This paper presents a new bit-parallel multiplier for the finite field GF(2^m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.
Index Terms- Bit-parallel multiplier, redundant representation, finite field arithmetic, AOP, Karatsuba method.
H. Cho, K. Chang and D. Hong, "Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation," in IEEE Transactions on Computers, vol. 54, no. , pp. 1628-1630, 2005.