Issue No. 12 - December (2005 vol. 54)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.196
James Chin , IEEE
Mehrdad Nourani , IEEE
We present a comprehensive and flexible test scheduling environment, called FITS, for testing core-based system-on-chips. Our environment prevents formation of hot spots during test. It also allows trade-off among test time, test access mechanism, power, and test controller/resource constraints. The basic strategy is to use power profile over application time and structural grids of nonembedded cores to find the best test schedule of their test pattern subsets while satisfying the constraints. As case studies, four integer linear programming formulations, corresponding to four power approximation models, are extensively analyzed. With proper setting of the weights and constraints, optimized results can be obtained quickly for each of the four power approximation models. Extensive experimental results are reported based on ISCAS '89 benchmarks and verify the efficiency and flexibility of the FITS environment.
Index Terms- Automatic test equipment, embedded core, grid, hot-spot, ILP formulation, power profile, system-on-chip, trade-off, test access mechanism, test schedule.
J. Chin and M. Nourani, "FITS: An Integrated ILP-Based Test Scheduling Environment," in IEEE Transactions on Computers, vol. 54, no. , pp. 1598-1613, 2005.