Issue No.12 - December (2005 vol.54)
Matthew W. Heath , IEEE
Wayne P. Burleson , IEEE
Ian G. Harris , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.203
This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "Synchro-Tokens.” Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of Synchro-Tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-Tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.
Index Terms- GALS, globally asynchronous locally synchronous, nondeterminism, debug, test, SoC.
Matthew W. Heath, Wayne P. Burleson, Ian G. Harris, "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test", IEEE Transactions on Computers, vol.54, no. 12, pp. 1532-1546, December 2005, doi:10.1109/TC.2005.203