Issue No. 08 - August (2005 vol. 54)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.134
Partha Pratim Pande , IEEE
André Ivanov , IEEE
Resve Saleh , IEEE
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.
Index Terms- Network-on-chip, MP-SoC, infrastructure IP, interconnect architecture, system-on-chip.
R. Saleh, M. Jones, A. Ivanov, P. P. Pande and C. Grecu, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," in IEEE Transactions on Computers, vol. 54, no. , pp. 1025-1040, 2005.