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Low-power embedded processors utilize compact instruction encodings to achieve small code size. Such encodings place tight restrictions on the number of bits available to encode operand specifiers and, thus, on the number of architected registers. As a result, performance and power are often sacrificed as the burden of operand supply is shifted from the register file to the memory due to the limited number of registers. In this paper, we investigate the use of a windowed register file to address this problem by providing more registers than allowed in the encoding. The registers are organized as a set of identical register windows where, at each point in the execution, there is a single active window. Special window management instructions are used to change the active window and to transfer values between windows. This design gives the appearance of a large register file without compromising the instruction encoding. To support the windowed register file, we designed and implemented a graph partitioning-based compiler algorithm that partitions program variables and temporaries referenced within a procedure across multiple windows. On a 16-bit embedded processor, an average of 11 percent improvement in application performance and 25 percent reduction in system power was achieved as an 8-register design was scaled from one to two windows.
Index Terms- Code generation, embedded processor, graph partitioning, instruction encoding, low-power design, optimization, retargetable compilers, register window, spill code.
Rajiv A. Ravindran, Robert M. Senger, Scott A. Mahlke, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Richard B. Brown, "Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor", IEEE Transactions on Computers, vol. 54, no. , pp. 998-1012, August 2005, doi:10.1109/TC.2005.132
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