Issue No. 07 - July (2005 vol. 54)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.117
Huiyang Zhou , IEEE
Thomas M. Conte , IEEE
The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow memory operations such as cache misses) significantly. Therefore, for memory-intensive workloads, it becomes more important to overlap multiple cache misses than to overlap slow memory operations with other computations. In this paper, we propose a novel technique to parallelize sequential cache misses, thereby increasing memory-level parallelism (MLP). Our idea is based on value prediction, which was proposed originally as an instruction-level parallelism (ILP) optimization to break true data dependencies. In this paper, we advocate value prediction in its capability to enhance MLP instead of ILP. We propose using value prediction and value-speculative execution only for prefetching so that not only the complex prediction validation and misprediction recovery mechanisms are avoided, but better performance can also be achieved for memory-intensive workloads. The minor hardware modifications that are required also enable aggressive memory disambiguation for prefetching. The experimental results show that our technique enhances MLP effectively and achieves significant speedups, even with a simple stride value predictor.
Index Terms- Single data stream architectures.
H. Zhou and T. M. Conte, "Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction," in IEEE Transactions on Computers, vol. 54, no. , pp. 897-912, 2005.