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Motion estimation is the most computationally expensive task in MPEG-style video compression. Video compression is starting to be widely used in battery-powered terminals, but surprisingly little is known about the power consumption of modern motion estimation algorithms. This paper describes our effort to analyze the power and performance of realistic motion estimation algorithms in both hardware and software realizations. For custom hardware realizations, this paper presents a general model of VLSI motion estimation architectures. This model allows us to analyze in detail the power consumption of a large class of modern motion estimation engines that can execute the motion estimation algorithms of interest to us. We compare these algorithms in terms of their power consumption and performance. For software realizations, this paper provides the first detailed instruction-level simulation results on motion estimation based on a programmable CPU core. We analyzed various aspects of the selected motion estimation algorithms, such as search speed and power distribution. This paper provides a guideline to two types of machine designs for motion estimation: custom ASIC (Application Specific Integrated Circuit) design and custom ASIP (Application Specific Instruction-set Processor) designs.
Motion estimation algorithm, power modeling, performance optimization.

W. Wolf, S. Yang and N. Vijaykrishnan, "Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations," in IEEE Transactions on Computers, vol. 54, no. , pp. 714-726, 2005.
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