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In this work, we propose a new algorithm for designing diminished-1 modulo 2^n+1 multipliers. The implementation of the proposed algorithm requires n+3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2^n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.
Modulo 2^n+1 multipliers, computer arithmetic, residue number system, Fermat number transform, VLSI design.

G. Dimitrakopoulos, H. T. Vergos, C. Efstathiou and D. Nikolos, "Efficient Diminished-1 Modulo 2^n+1 Multipliers," in IEEE Transactions on Computers, vol. 54, no. , pp. 491-496, 2005.
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