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Issue No. 03 - March (2005 vol. 54)
ISSN: 0018-9340
pp: 319-330
A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at
Computer arithmetic, elementary function evaluation, hardware operator, table lookup and addition method.

F. de Dinechin and A. Tisserand, "Multipartite Table Methods," in IEEE Transactions on Computers, vol. 54, no. , pp. 319-330, 2005.
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