Issue No. 03 - March (2005 vol. 54)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.41
Albert Danysh , IEEE
Dimitri Tan , IEEE
This paper presents a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64\times64, two 32\times32, four 16\times16, or eight 8\times8 bit signed/unsigned multiply-accumulates using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized” by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation” in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors. The "shared segmentation” method is compared to an alternative method, referred to as the "shared subtree” method, by implementing vector MAC designs using two different technologies and three different vector widths.
Parallel, high-speed arithmetic, multimedia, data-path design, VLSI, MAC, multiply-accumulate, multiplier, vector, SIMD, Booth, Wallace, signed, unsigned, integer, fixed-point.
A. Danysh and D. Tan, "Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit," in IEEE Transactions on Computers, vol. 54, no. , pp. 284-293, 2005.