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We present a high-performance low-power design of linear array multipliers based on a combination of the following techniques: signal flow optimization in [3:2] adder array for partial product reduction, left-to-right leapfrog (LRLF) signal flow, and splitting of the reduction array into upper/lower parts. The resulting upper/lower LRLF (ULLRLF) multiplier is compared with tree multipliers. From automatic layout experiments, we find that ULLRLF multipliers have similar power, delay, and area as tree multipliers for n \leq 32. With more regularity and inherently shorter interconnects, the ULLRLF structure presents a competitive alternative to tree structures in the design of fast low-power multipliers implemented in deep submicron VLSI technology.
Left-to-right array multiplier, tree multiplier, high-performance design, low-power design, layout regularity.

Z. Huang and M. D. Ercegovac, "High-Performance Low-Power Left-to-Right Array Multiplier Design," in IEEE Transactions on Computers, vol. 54, no. , pp. 272-283, 2005.
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