Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests
Issue No. 12 - December (2004 vol. 53)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.118
Irith Pomeranz , IEEE
Sudhakar M. Reddy , IEEE
A new class of static compaction procedures is described that generate test sets with reduced test application times for scan circuits. The proposed class of procedures combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with a short primary input sequence included in every test and one that tends to generate small numbers of tests with a long primary input sequence included in one of the tests. A procedure of the proposed class starts from an initial test set that has a large number of tests and long primary input sequences and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time. Several ways of computing the primary input sequences for the initial test set are considered. The most compact test sets are obtained when a test sequence for the nonscan circuit is available and this sequence is used as part of every test in the initial test set. However, it is shown that high levels of compaction can also be achieved without the overhead of test generation for the nonscan circuit. Specifically, we show that the industry practice of holding a primary input vector constant between scan operations can be accommodated. We estimate the ability of the procedure to achieve optimum test sets by computing a lower bound on the number of tests and demonstrating that the procedure achieves or approaches this lower bound.
Scan circuits, static test compaction, test application time.
Irith Pomeranz, Sudhakar M. Reddy, "Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests", IEEE Transactions on Computers, vol. 53, no. , pp. 1569-1581, December 2004, doi:10.1109/TC.2004.118