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The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis tools since that allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous work, however, neglects the delay of interconnects (e.g. multiplexers) which can heavily influence the overall performance of the design. In addition, in the case of dynamic reconfigurable logic circuits, unless an appropriate design methodology is followed, an unnecessarily large number of configurable logic blocks may end up being used for communication between contexts, rather than for implementing function units. The aim of this paper is to present a new technique to perform interconnect-sensitive synthesis, targeting dynamic reconfigurable circuits. Further, the proposed technique exploits multiple hardware contexts to achieve efficient designs. Experimental results on several benchmarks, which have been done on our DRL LSI circuit [10], [12], demonstrate that, by jointly optimizing the interconnect, communication, and function unit cost, we can achieve higher quality designs than is possible with such previous techniques as Force-Directed Scheduling.
Dynamic reconfigurable logic, scheduling, allocation, partitioning, communication cost.

M. Motomura and M. Meribout, "A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems," in IEEE Transactions on Computers, vol. 53, no. , pp. 1508-1522, 2004.
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