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By adapting to computations that are not so well-supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application. A great deal of the research effort in this area is aimed at accelerating the solution of combinatorial optimization problems. Special attention in this context was given to the Boolean satisfiability (SAT) problem resulting in a considerable number of different architectures being proposed. This paper presents the state-of-the-art in reconfigurable hardware SAT satisfiers. The analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity, and performance.
Boolean satisfiability, reconfigurable computing, FPGA, hardware acceleration.
Iouliia Skliarova, António de Brito Ferrari, "Reconfigurable Hardware SAT Solvers: A Survey of Systems", IEEE Transactions on Computers, vol. 53, no. , pp. 1449-1461, November 2004, doi:10.1109/TC.2004.102
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