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Issue No. 11 - November (2004 vol. 53)
ISSN: 0018-9340
pp: 1363-1375
In this paper, we present a polymorphic processor paradigm incorporating both general purpose and custom computing processing. The proposal incorporates an arbitrary number of programmable units, exposes the hardware to the programmers/designers, and allows them to modify and extend the processor functionality at will. To achieve the previously stated attributes, we present a new programming paradigm, a new instruction set architecture, a microcode-based microarchitecture, and a compiler methodology. The programming paradigm, in contrast with the conventional programming paradigms, allows general-purpose conventional code and hardware descriptions to coexist in a program. In our proposal, for a given instruction set architecture, a one-time instruction set extension of eight instructions is sufficient to implement the reconfigurable functionality of the processor. We propose a microarchitecture based on reconfigurable hardware emulation to allow high-speed reconfiguration and execution. To prove the viability of the proposal, we experimented with the MPEG-2 encoder and decoder and a Xilinx Virtex II Pro FPGA. We have implemented three operations, SAD, DCT, and IDCT. The overall attainable application speedup for the MPEG-2 encoder and decoder is between 2.64-3.18 and between 1.56-1.94, respectively, representing between 93 percent and 98 percent of the theoretically obtainable speedups.
Custom computing machines, FPGA, firmware, reconfigurable microcode, polymorphic processors, reconfigurable processors.

S. Wong, G. Kuzmanov, E. Moscu Panainte, S. Vassiliadis, K. Bertels and G. Gaydadjiev, "The MOLEN Polymorphic Processor," in IEEE Transactions on Computers, vol. 53, no. , pp. 1363-1375, 2004.
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