Issue No. 09 - September (2004 vol. 53)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.60
Haridimos T. Vergos , IEEE
Dimitris Nikolos , IEEE
Modulo 2^n+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2^n+1 adders, based on parallel-prefix carry computation units. The first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.
Binary adders, modulo 2^n+1 arithmetic, parallel-prefix adders, RNS.
C. Efstathiou, D. Nikolos and H. T. Vergos, "Fast Parallel-Prefix Modulo 2^n+1 Adders," in IEEE Transactions on Computers, vol. 53, no. , pp. 1211-1216, 2004.