Issue No. 08 - August (2004 vol. 53)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.44
Tom? Lang , IEEE Computer Society
Javier D. Bruguera , IEEE
<p><b>Abstract</b>—We propose an architecture for the computation of the double-precision floating-point multiply-add-fused (MAF) operation <tmath>A + (B \times C)</tmath>. This architecture is based on the combined addition and rounding (using a dual adder) and in the anticipation of the normalization step before the addition. Because the normalization is performed before the addition, it is not possible to overlap the leading-zero-anticipator with the adder. Consequently, to avoid the increase in delay, we modify the design of the LZA so that the leading bits of its output are produced first and can be used to begin the normalization. Moreover, parts of the addition are also anticipated. We have estimated the delay of the resulting architecture considering the load introduced by long connections, and we estimate a delay reduction of between 15 percent and 20 percent, with respect to previous implementations.</p>
Computer arithmetic, floating-point functional units, multiply-add-fused (MAF) operation, VLSI design.
Tom? Lang, Javier D. Bruguera, "Floating-Point Multiply-Add-Fused with Reduced Latency", IEEE Transactions on Computers, vol. 53, no. , pp. 988-1003, August 2004, doi:10.1109/TC.2004.44