Issue No. 07 - July (2004 vol. 53)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.20
Nak-Woong Eum , IEEE
Taewhan Kim , IEEE
Chong-Min Kyung , IEEE
<p><b>Abstract</b>—This paper presents a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: <it>inaccurate estimations of routing density</it> that were too general for symmetrical FPGAs. To this end, we formulate an <it>exact routing density calculation</it> that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called <it>cost-effective net-decomposition-based routing</it>, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics.</p>
FPGAs, routing algorithms, performance, routability, routing density.
C. Kyung, N. Eum and T. Kim, "CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation," in IEEE Transactions on Computers, vol. 53, no. , pp. 829-842, 2004.