Issue No. 06 - June (2004 vol. 53)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.11
Dmitry Ponomarev , IEEE
Gurhan Kucuk , IEEE
Oguz Ergin , IEEE
Kanad Ghose , IEEE
<p><b>Abstract</b>—A mechanism for reducing the power requirements in processors that use a separate (architectural) register file (ARF) for holding committed values is proposed in this paper. We exploit the notion of short-lived operands—values that target architectural registers that are renamed by the time the instruction producing the value reaches the writeback stage. Our simulations of the SPEC 2000 benchmarks show that as much as 71 percent to 97 percent of the results are short-lived. Our technique avoids unnecessary writebacks into the result repository (a slot within the Reorder Buffer or a physical register) as well as writes into the ARF from unnecessary commitments by caching (and isolating) short-lived operands within a small dedicated register file. Operands are cached in this manner till they can be safely discarded without jeopardizing the recovery from possible branch mispredictions or reconstruction of the precise state in case of interrupts or exceptions. Additional energy savings are achieved by limiting the number of ports used for instruction commitment. The power/energy savings are validated using SPICE measurements of actual layouts in a 0.18 micron CMOS process. The energy reduction in the ROB and the ARF is about 20 percent (translating into the overall chip energy reduction of about 5 percent) and this is achieved with no increase in cycle time, little additional complexity, and no degradation in the number of instructions committed per cycle.</p>
Short-lived operands, superscalar datapath, energy reduction.
G. Kucuk, O. Ergin, K. Ghose and D. Ponomarev, "Isolating Short-Lived Operands for Energy Reduction," in IEEE Transactions on Computers, vol. 53, no. , pp. 697-709, 2004.