Issue No. 05 - May (2004 vol. 53)

ISSN: 0018-9340

pp: 628-640

Katarzyna Radecka , IEEE

Zeljko Zilic , IEEE

ABSTRACT

In this paper, we investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the Arithmetic Transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the Universal Test Set (UTS) approach to test vector generation. The major result in this paper shows that, for errors whose AT has at most <tmath>t</tmath> nonzero coefficients, there exist the UTS test vector set of size <tmath>O(n^{log t}_2)</tmath>. Consequently, verification confidence can be parameterized by the size of the error <tmath>t</tmath>, where at most <tmath>O(n^{log t}_2)</tmath> verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the Arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.

INDEX TERMS

Verification, error modeling, spectral methods, arithmetic transform, Walsh-Hadamard transform, Reed-Muller transform, Universal Test Set.

CITATION

K. Radecka and Z. Zilic, "Design Verification by Test Vectors and Arithmetic Transform Universal Test Set," in

*IEEE Transactions on Computers*, vol. 53, no. , pp. 628-640, 2004.

doi:10.1109/TC.2004.1275301

CITATIONS