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Issue No. 04 - April (2004 vol. 53)
ISSN: 0018-9340
pp: 439-452
ABSTRACT
In order to reduce the memory access time for a Single-Instruction Multiple-Data stream (SIMD) computer with <it>pq</it> processing elements attached to a host computer, a multiaccess memory system is proposed in this paper. The proposed memory system supports simultaneous access to <it>pq</it> data elements within a 4-directional block (p × q), a row (1 × pq), a column (pq × 1), a forward-diagonal, and a backward-diagonal subarray with a constant interval in an arbitrary position in an <it>M</it>×<it>N</it> array of data elements, where the number of memory modules, <it>m</it>, is a prime number greater than <it>pq</it>. For the simple and fast address calculation and routing circuit, the address differences between the <it>pq</it> addresses and the base address are arranged in ascending order according to the index numbers of <it>m</it> memory modules from the index number of memory module of the first element. The proposed multiaccess memory system provides more subarray types and more constant intervals than the previous memory systems.
INDEX TERMS
SIMD computer, prime memory system, multiaccess memory system, conflict-free memory system, address calculation, routing circuit.
CITATION
Jong Won Park, "Multiaccess Memory System for Attached SIMD Computer", IEEE Transactions on Computers, vol. 53, no. , pp. 439-452, April 2004, doi:10.1109/TC.2004.1268401
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