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<p><b>Abstract</b>—Partial scan design is divided into two stages: 1) critical cycle breaking and 2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. The valid-state-based testability measure may become ineffective to select scan flip-flops when cycles remaining in the circuit are not so influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure <it>conflict</it>. Sufficient experimental results are presented.</p>
Valid state, partial scan design, invalid state, conflict, testability measure, testability improvement potential.

D. Xiang and J. H. Patel, "Partial Scan Design Based on Circuit State Information and Functional Analysis," in IEEE Transactions on Computers, vol. 53, no. , pp. 276-287, 2004.
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