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<p><b>Abstract</b>—In this paper, we present new design methods for modulo 2<SUP>n</SUP>± 1 adders. We use the same select-prefix addition block for both modulo 2<SUP>n</SUP> - 1 and diminished-one modulo 2^n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.</p>
modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures.
Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou, "Modulo 2<sup>n</sup> ± 1 Adder Design Using Select-Prefix Blocks", IEEE Transactions on Computers, vol. 52, no. , pp. 1399-1406, November 2003, doi:10.1109/TC.2003.1244938
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