Issue No. 08 - August (2003 vol. 52)
Hideo Fujiwara , IEEE
Dong Xiang , IEEE
<p><b>Abstract</b>—A testability measure called <it>conflict</it> based on conflict analysis in the process of sequential circuit test generation is introduced to guide nonscan design for testability. The testability measure indicates the number of potential conflicts to occur or the number of clock cycles required to detect a fault. A new testability structure is proposed to insert control points by switching the extra inputs to primary inputs, using whichever extra inputs of all control points can be controlled by independent signals. The proposed design for testability approach is economical in delay, area, and pin overheads. The nonscan design for testability method based on the <it>conflict</it> measure can reduce many potential backtracks and make many hard-to-detect faults easy-to-detect; therefore, it can enhance actual testability of the circuit greatly. Extensive experimental results are presented to demonstrate the effectiveness of the method.</p>
Conflict, inversion parity, nonscan design for testability, partial scan design, sequential depth for testability, testability measure.
Hideo Fujiwara, Dong Xiang, Yi Xu, "Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution", IEEE Transactions on Computers, vol. 52, no. , pp. 1063-1075, August 2003, doi:10.1109/TC.2003.1223640