Issue No. 03 - March (2003 vol. 52)
Suleyman Sair , IEEE
Timothy Sherwood , IEEE
Brad Calder , IEEE
<p><b>Abstract</b>—An effective method for reducing the effect of load latency in modern processors is data prefetching. One form of hardware-based data prefetching, stream buffers, has been shown to be particularly effective due to its ability to detect data streams and run ahead of them, prefetching as it goes. Unfortunately, in the past, the applicability of streaming was limited to stride intensive code. In this paper, we propose <it>Predictor-Directed Stream Buffers</it> (<it>PSB</it>), which allows the stream buffer to follow a general address prediction stream instead of a fixed stride. A general address prediction stream complicates the allocation of both stream buffer and memory resources because the predictions generated will not be as reliable as prior sequential next-line and stride-based stream buffer implementations. To address this, we examine using confidence-based techniques to guide the allocation and prioritization of stream buffers and their prefetch requests. Our results show, when using PSB on a benchmark suite heavy in pointer-based applications, that PSB provides a 23 percent speedup on average over the best previous stream buffer implementation, and an improvement of 75 percent over using no prefetching at all.</p>
Data prefetching, stream buffers, address prediction.
T. Sherwood, B. Calder and S. Sair, "A Decoupled Predictor-Directed Stream Prefetching Architecture," in IEEE Transactions on Computers, vol. 52, no. , pp. 260-276, 2003.