ABSTRACT

<p><b>Abstract</b>—An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a routing requirement over the switch box. Comparing with the known “universal switch modules,” where only 2-pin nets are considered, the hyper-universal switch box model is more general and powerful. This paper studies the generic problem and proposes a systematic designing methodology for hyper-universal <tmath>(k, W){\hbox{-}}{\rm switch}</tmath> boxes, where <tmath>k</tmath> is the number of sides and <tmath>W</tmath> is the number of terminals on each side. We formulate this hyper-universal <tmath>(k, W){\hbox{-}}{\rm switch}</tmath> box design problem as a <tmath>k{\hbox{-}}{\rm partite}</tmath> graph design problem and propose an efficient reduction design technique. Applying this technique, we can design hyper-universal <tmath>(k, W){\hbox{-}}{\rm switch}</tmath> boxes with low <tmath>O(W)</tmath> switches for any fixed <tmath>k</tmath>. For illustration, we provide optimum hyper-universal <tmath>(2, W)</tmath> and <tmath>(3, W){\hbox{-}}{\rm switch}</tmath> boxes and a hyper-universal <tmath>(4, W){\hbox{-}}{\rm switch}</tmath> box with switch number quite close to the lower bound <tmath>6W</tmath>, which is used in a well-known commercial design without hyper-universal routability. We also conclude that the proposed reduction method can yield an efficient detailed routing algorithm for any given routing requirement as well.</p>

INDEX TERMS

FPGA, switch box, global routing, detailed routing, hyper-universal, optimum design, reduction technique.

CITATION

J. Liu, Y. Wu and H. Fan, "General Models and a Reduction Design Technique for FPGA Switch Box Designs," in

*IEEE Transactions on Computers*, vol. 52, no. , pp. 21-30, 2003.

doi:10.1109/TC.2003.1159751

CITATIONS