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<p>We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T_0 and ensuring that every fault detected by T_0 is detected by the expanded version of at least one loaded sequence. Specifically, each input sequence S is constructed based on a different fault f and is extracted from T_0 around a time unit where f is detected by T_0. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored on-chip at any given time is, on the average, 11 percent of the length of T_0 and that the total length of all the loaded sequences is, on the average, 48 percent of the length of T_0. These results are obtained by extracting each sequence S around the <it>first</it> detection time of a target fault f. These results are further improved by considering several time units for every target fault f and selecting the shortest possible sequence based on f.</p>
at-speed testing, built-in test generation, synchronous sequential circuits

S. Reddy and I. Pomeranz, "Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times," in IEEE Transactions on Computers, vol. 51, no. , pp. 409-419, 2002.
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