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<p><b>Abstract</b>—Loops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations per cycle, current processors are designed with growing degrees of resource replication (<it>replication technique</it>) for memory ports and functional units. However, the high cost in terms of area and cycle time of this technique precludes the use of high degrees of replication. High values for the cycle time may clearly offset any gain in terms of number of execution cycles. High values for the area may lead to an unimplementable configuration. An alternative to resource replication is resource widening (<it>widening technique</it>), which has also been used in some recent designs in which the width of the resources is increased (i.e., a single operation is performed over multiple data). Moreover, several general-purpose superscalar microprocessors have been implemented with multiply-add fused floating-point units (<it>fusion technique</it>), which reduces the latency of the combined operation and the number of resources used. In this paper, we evaluate a broad set of VLIW processor design alternatives that combine the three techniques. We perform a technological projection for the next processor generations in order to foresee the possible implementable alternatives. From this study, we conclude that if the cost is taken into account, combining certain degrees of replication and widening in the hardware resources is more effective than applying only replication. Also, we confirm that multiply-add fused units will have a significant impact in raising the performance of future processors architectures with a reasonable increase in cost.</p>
VLIW processors, instruction level parallelism, software pipelining, numerical applications, performance/cost trade-off.

M. Valero, J. Llosa, D. López and E. Ayguadé, "Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures," in IEEE Transactions on Computers, vol. 50, no. , pp. 1033-1051, 2001.
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