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<p><b>Abstract</b>—VLSI-based processor arrays have been widely used for computation intensive applications such as matrix and graph algorithms. <it>Algorithm-based fault tolerance</it> designs employing various encoding/decoding schemes have been proposed for such systems to effectively tolerate operation time fault. In this paper, we propose an efficient algorithm-based fault tolerance design using the weighted data-check relationship, where the checks are obtained from the weighted data. The relationship is systematically defined as a new <tmath>$(n,k,N_w)$</tmath> Hamming checksum code, where <tmath>$n$</tmath> is the size of the code word, <tmath>$k$</tmath> is the number of information elements in the code word, and <tmath>$N_w$</tmath> is the number of weights employed, respectively. The proposed design with various weights is evaluated in terms of time and hardware overhead as well as overflow probability and round-off error. Two different schemes employing the <tmath>$(n,k,2)$</tmath> and <tmath>$(n,k,3)$</tmath> Hamming checksum code are illustrated using important matrix computations. Comparison with other schemes reveals that the <tmath>$(n,k,3)$</tmath> Hamming checksum scheme is very efficient, while the hardware overhead is small.</p>
Algorithm-based fault tolerance, Hamming correcting code, matrix computations, overflow, round-off error, VLSI processor array.

D. Lee, H. Choo, H. Y. Youn, J. Chung and C. G. Oh, "An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship," in IEEE Transactions on Computers, vol. 50, no. , pp. 371-383, 2001.
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